In a conventional double data rate (DDR) synchronous dynamic random access memory (SDRAM) to application specific integrated circuit (ASIC) interface, incoming data is accompanied with a strobe signal. The strobe signal has a fixed (but unknown) phase relation with a local clock. The strobe signal needs to be synchronized with the local clock for stable data transaction. The round trip delay is the time between the issue of a command to the arrival of data from the SDRAM. The round trip delay also needs to be known to determine when the real data starts.
Conventional systems implement an on-board delay line or an on-chip PLL to synchronize the strobe signal with the local clock. The round trip delay is calculated during the system setup. However, the round trip delay calculation becomes less reliable as data rates increase and as process, voltage and temperature (PVT) variations become significant compared with the clock cycle time.